The present invention relates in general to memory access in a computer system and more particularly to a method and apparatus for analyzing buffer allocation to a device on a peripheral component interconnect bus.
In large computer systems, input/output access to memory has higher latency than a simple computer architecture for which a peripheral component interconnect bus was intended. This latency is due to the computer system having several memory subsystems connected via an interconnect network which requires some amount of time to traverse. Memory latency is dependent on the amount of hardware between the input/output subsystem and the memory subsystem. In most computer systems, memory is accessed in cache line units and is quantized or packetized to these units. Peripheral component interconnect bus implementations do not packetize its operation but expect that the bus has sole access to memory. By having sole access to memory, packetization of data is not required because any cache operations can be processed directly. Bandwidth falls short for fiber channel and other high bandwidth devices with only a single request in flight. Multiple requests in flight are needed for any given burst from the peripheral component interconnect bus. Since the peripheral component interconnect bus does not provide any indication as to the size of a transfer, the system input/output hardware must speculate on the access and pre-fetch of data ahead of the most current access and thus minimize the latency of sequential requests. Speculation requires additional system hardware resources and generates additional memory accesses, both adding to the total cost of the computer system. Therefore, it is desirable to optimize the amount of speculation that must be performed in accessing memory.
From the foregoing, it may be appreciated that a need has arisen for a technique to analyze allocation of resources in a computer system in order to optimize speculation required to access memory. In accordance with the present invention, a method and apparatus for analyzing buffer allocation to a device on a peripheral component interconnect bus are provided that substantially eliminate or reduce disadvantages and problems associated with conventional memory access techniques in a computer system.
According to an embodiment of the present invention, there is provided a method of analyzing buffer allocation to a device on a peripheral component interconnect bus that includes receiving a request for data from the device. A check is made to a buffer to determine whether the data is present. If not present, the data is retrieved from memory and includes retrieving speculative data pre-fetched in anticipation of its use by the device. Retry commands are issued to the device, causing the device to re-request the data, until requested data is received in the buffer. A first counter is incremented each time data in the buffer is provided to the device. A second counter is incremented each time data in the buffer is not accessed by the device. A third counter is periodically incremented upon initiating retrieval of the data until the data is received in the buffer from the memory. The third counter determines a retrieval latency for all requests made by the device and an average retrieval latency may be determined from the first, second, and third counters.
The present invention provides various technical advantages over conventional memory access techniques. For example, one technical advantage is to analyze buffer usage in a computer system. Another technical advantage is to adjust the allocation of a buffer in response to measured usage parameters. Yet another technical advantage is to optimize memory access speculation without introducing additional hardware into the computer system. Still another technical advantage is to adjust pre-fetch depth for memory retrievals. Other technical advantages may be readily apparent to those skilled in the art from the following figure, description, and claims.